收藏本站
List of Document Changes
The following table lists critical changes that were made in the current version of the document.
H
Previous
Version
v4.0
(November 2013)
v3.2
v3.1
Changes in Current Version (v4.0)
The “Clocking in SmartFusion2” section is added and “Pin Assignments” section is updated in
“Implementation Hints” chapter.
The core version was updated to v3.6.
The “Tool Flows” chapter was revised to remove licensing information and add SmartDesign instructions.
Figure 3-1 · CorePCIF Configuration in SmartDesign through Figure 3-3 · CorePCIF Configuration in
SmartDesign (continued are new.
The “Stitching and Generation” section was removed from the “Tool Flows” chapter. The “Importing into
Libero IDE” and “Simulation Flows” sections were removed. The “Synthesis in Libero IDE” section was
revised to remove references to CoreConsole.
ProASIC3L was added to the possible values of the Family parameter in Table 4-1 · General Parameters .
The description for the USE_REGISTERS parameter was revised.
The description for the DMA_REG_LOC parameter value of 0 was revised in Table 4-4 · Master/DMA
Parameters .
The USE_GLOBAL_CLK and STALL_MODE parameters were added to Table 4-5 · Default Build
Parameters1 .
The following tables were renamed to better distinguish them from one another:
Table 5-1 · PCI Bus Interface Signals
Table 5-3 · Dataflow Interface Signals
Table 5-4 · Target Mode Control Signals
Table 5-5 · Master Mode Signals
A cautionary note was added for the SERRN_OUT signal in Table 5-2 · System-Level Signals . The
INTAN_OUT signal was added to Table 5-4 · Target Mode Control Signals .
The “STALL_MASTER Operation” section was revised to include “with STALL_MODE = 0” in
parentheses, for clarification.
The “Axcelerator and RTAX-S Families” section was revised to include information about meeting PCI
track lengths with the planned pinout and FPGA location on the PCB.
The core version was changed to v3.5.
The utiliziation values were updated in Table 2 · 32-Bit CorePCIF Device Utilization and Table 3 · 64-Bit
CorePCIF Device Utilization .
ProASIC3L was added to Table 2 · 32-Bit CorePCIF Device Utilization and Table 3 · 64-Bit CorePCIF
Device Utilization . Table 4 · Device Speed Grade Requirements , Table 7 · Supported Electrical
Environments , and Table 3-1 · Designer Compile Options were updated to change ProASIC3/E to
ProASIC3/E/L where appropriate.
Figure 2-1 · CorePCIF Structure was revised to remove cm8dxe2. Table 2-2 · Technology-Specific Source
Files was updated to remove the cm8dxe2 file.
Figure 3-1 · CorePCIF Configuration and Figure 3-2 · CorePCIF Configuration (continued) were
updated.
The “Ordering Information” chapter was added.
v4.0
Page
127
N/A
29
29
35
39
40
44
94
130
6
7 , 8
7 – 9 ,
13 , 34
25 , 27
28 , 29
147
149
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
COREU1LL-AR IP MODULE COREU1LL
COREU1PHY-AR IP MODULE COREU1PHY
CORR-8BIT-XM-UT2 SITE LICENSE IP CORRELATOR XP
CP2-GSA-L CONN SHIELD LOWER TYPE A 22
CP2-HSA110-1 CONN SHROUD CPCI 2MM TYPE A 22
CP2-HSC055-4 CONN SHROUD CPCI 2MM TYPE C 11
CP2-K3567-SR-F COMPACT PCI - MISC
CP2105EK KIT EVAL FOR CP2105
相关代理商/技术参数
COREPCIF-RMFL 功能描述:IP MODULE 制造商:microsemi corporation 系列:- 零件状态:在售 类型:许可证 应用:- 版本:- 许可长度:- 许可 - 用户明细:- 操作系统:- 配套使用产品/相关产品:Microsemi 器件 媒体分发类型:- 标准包装:1
COREPCIF-UR 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1
COREPCI-SN 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-SR 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-UR 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-XX 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPRO LEDBULB 10.5-60W B 制造商:Philips Lumileds 功能描述:
COREPRO LEDBULB 10.5-60W E 制造商:Philips Lumileds 功能描述: